1. Field of the Invention
The present invention relates .to a differential amplifier and more specifically to a differential amplifier of wide dynamic range.
2. Description of the Prior Art
An example of prior-art differential amplifiers is disclosed in U.S. Pat. No. 4,600,893 of the same inventor, for instance, which is incorporated herein by reference.
FIG. 1 shows a differential amplifier disclosed in this U.S. Patent. In the drawing, the differential amplifier roughly comprises a pair of NPN input transistors Q.sub.1 and Q.sub.2 ; a current mirror circuit 60, and a pair of PNP output transistors Q.sub.5 and Q.sub.6. Two base terminals 1 and 2 of the transistors Q.sub.1 and Q.sub.2 are two input terminals of the differential amplifier. A voltage difference S.sub.i between the first and second voltage signals applied to the gates of Q.sub.1 and Q.sub.2 is amplified by the differential amplifier. Two resistors R.sub.1 and R.sub.2 are connected in series between the two emitters of the transistors Q.sub.1 and Q.sub.2 and a constant current source I is connected between a junction point between R.sub.1 and R.sub.2 and ground. Two collectors of the transistors Q.sub.1 and Q.sub.2 are connected to a supply voltage V.sub.cc via two resistors R.sub.5 and R.sub.6, respectively and to two emitters of the PNP transistors Q.sub.5 and Q.sub.6, respectively. Two collectors of the transistors Q.sub.5 and Q.sub.6 are connected to the current mirror circuit 60. Two base terminals of the transistors Q.sub.5 and Q.sub.6 are connected in common to a first bias voltage V.sub.B. Further, only the collector of Q.sub.6 is connected to an output terminal 61, and a resistor R.sub.63 is connected between the terminal 61 and the ground. The current mirror circuit 60 is composed of an NPN transistor Q.sub.61 having the base and the collector connected to each other and to the collector of Q.sub.5 and an NPN transistor Q.sub.62 having the collector connected to the collector of Q.sub.6. Further, two resistors R.sub.61 and R.sub.62 are connected between the emitters of Q.sub.62 and Q.sub.61 and ground, respectively.
A supply voltage is applied between a first potential terminal (e.g. ground) and a second potential terminal (e.g. V.sub.cc), in FIG. 1.
In the prior-art differential amplifier shown in FIG. 1, currents flowing through the transistors Q.sub.5 and Q.sub.6 are controlled on the basis of a differential input signal S.sub.i applied between two input terminals 1 and 2. That is, when potential at the input terminal 1 is higher than that at the input terminal 2, the collector current flowing through the transistor Q.sub.1 is larger than that flowing through the transistor Q.sub.2. However, since current flowing through the resistor R.sub.5 or R.sub.6 is constant, the collector current flowing through the transistor Q.sub.6 is higher than that flowing through the transistor Q.sub.5, so that an output current flows through the output terminal 61 to rise the potential of the output signal S.sub.0.
In this case, when the transistors Q.sub.5 and Q.sub.6 are kept unsaturated, the potential of the output signal S.sub.0 cannot rise beyond the first bias voltage V.sub.B, as shown in FIG. 2.
On the other hand, when the potential at the input terminal 1 is lower than that at the input terminal 2, the collector current of the transistor Q.sub.6 is smaller than that of the transistor Q.sub.5. Therefore, current flows from the output terminal 61 to the transistor Q.sub.62, so that the potential of the output signal S.sub.0 drops.
In this case, when the transistors Q.sub.5 and Q.sub.6 are kept unsaturated, the potential of the output signal S.sub.0 cannot drop below V.sub.BE62 +R.sub.62, where V.sub.BE62 denotes a voltage between the base and the emitter of the transistor Q.sub.62 and R.sub.62 denotes a voltage drop across R.sub.62, as shown in FIG. 2.
Further, when this differential amplifier is operated at high speed under the condition that the two input transistors Q.sub.1 and Q.sub.2 are unsaturated, the level of the input signal is limited below (V.sub.cc -V.sub.5) or (V.sub.cc -V.sub.6), where V.sub.5 or V.sub.6 denotes a voltage drop across the resistor R.sub.5 or R.sub.6.
In addition, since the two input transistors Q.sub.1 and Q.sub.2 are composed of bipolar transistors, there exists another problem in that base current should be passed through each input transistor Q.sub.1 or Q.sub.2.
In summary, in the prior-art differential amplifier as shown in FIG. 1, there exist various drawbacks as follows:
(1) When the amplifier is operated at high speed under unsaturated conditions, the upper limit of the output signal S.sub.0 is V.sub.B or (V.sub.cc -V.sub.6 -V.sub.BE6) and the lower limit thereof is V.sub.BE62 +V.sub.62 as shown in FIG. 2. Therefore, the output dynamic range is narrow, so that his amplifier is not usable when a high output signal level of V.sub.cc or a low output signal level of GND is required.
(2) Since the two input transistors Q.sub.1 and Q.sub.2 are bipolar transistors, base currents are required as the input currents of the transistors Q.sub.1 and Q.sub.2. Therefore, a driver circuit of relatively high power is required to be connected to the input terminals 1 and 2 of the differential amplifier.